1. Field of the Invention
The present invention relates to a semiconductor device in which an insulated gate bipolar transistor and a control circuit are formed on a same semiconductor substrate. In particular, it relates to a construction of a protection device or protection circuit for preventing latch-up due to a parasitic device which occurs on the occasion of forming the control circuit on the insulated gate bipolar transistor using the joining and separating technique.
2. Description of the Prior Art
In general, when a circuit region or circuit element etc. is formed on a semiconductor substrate in which an insulated gate bipolar transistor (Hereinafter, it will be referred to xe2x80x9cIGBTxe2x80x9d.) is formed, a parasitic device which deteriorates the properties of the circuit, may occur. Therefore it has been tried to provide various methods of forming the circuit region or circuit element etc. which can restrain the action of the parasitic device.
For example, in the technical field for forming the circuit region by means of the joining and separating technique without using a particular technique for forming the substrate, a method of forming the above-mentioned circuit region or circuit device etc. is disclosed in the technical document of xe2x80x9cA Self-isolated Intelligent IGBT for Driving Ignition Coils (International Symposium on Power Semiconductor Drives and Ics, 1998)xe2x80x9d published in 1998. In the technical document, there is disclosed such a means for preventing a breakdown of the device by using a circuit in which a resistor and a diode formed on a polycrystalline silicon layer are combined, in order to avoid the breakdown of the circuit due to the action of a parasitic thyristor which may cause a fatal problem in the joining and separating technique.
Meanwhile, in each of the Japanese Laid-open Patent Publications No. 7-169963, No. 8-306924 and No. 64-51664 also, there is disclosed a technique for restraining the action of a parasitic device in a semiconductor device provided with an IGBT or MOSFET.
In FIG. 9, there is partially shown a conventional circuit for preventing the action of a parasitic thyristor, which is disclosed in the above-mentioned technical document. In FIG. 9, P1 denotes an input terminal for controlling a semiconductor device B2 in which a control circuit B1 is formed on a semiconductor substrate in which an IGBT Z1 is formed. P2 denotes an emitter terminal of the IGBT Z1, which acts as the ground terminal of the control circuit B1 also. P3 denotes a collector terminal of the IGBT Z1.
The input terminal P1 is connected to the cathode of a Zener diode D1 through a resistor R1. On the other hand, the anode of the Zener diode D1 is connected to the emitter terminal P2. Further the cathode of the Zener diode D1 is also connected to one end portion of a resistor R2. The other end portion of the resistor R2 is connected to one end portion of a resistor R3 and to the cathode of a Zener diode D8. The other end portion of the resistor R3 is connected to the control circuit B1. Meanwhile the anode of the Zener diode D8 is connected to the emitter terminal P2.
Each of the resistors R2, R3 and the diodes D1, D8 is formed on a polycrystalline silicon layer (Hereinafter, it will be referred to xe2x80x9cpolysilicon layerxe2x80x9d.) formed above the substrate in which the IGBT Z1 is formed, while interposing an insulating film therebetween. In the device described in the above-mentioned technical document, the control circuit B1 for controlling the IGBT Z1 is composed of a nch-MOSFET (of enhancement mode or depletion mode)
In FIG. 10, there is shown a construction each of parasitic thyristors of a circuit device in the conventional semiconductor device described above. As shown in FIG. 10, parasitic transistors T1, T2 are formed between each of diffused layers of an nch-MOSFET M and a semiconductor substrate U composing the diffused layers. A pxe2x88x92 type diffused region corresponding to the back gate G of the nch-MOSFET M, an n type diffused layer formed so as to be included in this pxe2x88x92 type diffused region (It corresponds to the source S or drain A of the nch-MOSFET M) and an nxe2x88x92 type layer of the semiconductor substrate U act as the base, emitter and collector of the npn type parasitic transistor T2, respectively. Meanwhile, a p type layer of the semiconductor substrate U, n+ and nxe2x88x92 type layers formed on this p type layer and a pxe2x88x92 type diffused layer corresponding to the back gate G of the nch-MOSFET M act as the emitter, base and collector of the pnp type parasitic transistor T1, respectively.
The parasitic transistors T1, T2 become such a state that the collector of the parasitic transistor T1 is connected to the base of the parasitic transistor T2 while the base of the parasitic transistor T1 is connected to the collector of the parasitic transistor T2, so that a thyristor is formed. In consequence, if the thyristor has become ON state once, it is impossible to make the thyristor become OFF state except making such a state that the collector potential of the IGBT M becomes lower than the emitter potential of the IGBT M.
As patterns that the thyristor becomes ON state, the following two patterns may be estimated. One is such a case that the source potential of the nch-MOSFET M becomes lower than the back gate potential so that emitter current is generated in the npn type parasitic transistor T1. The other is such a case that the pnp type parasitic transistor T1 becomes ON state in accordance with the ON state of the IGBT M formed on the same substrate. In this case, the collector current of the pnp type parasitic transistor T1 flows into the back gate G of the nch-MOSFET M so that the potential of the back gate G is lowered. In consequence, when it becomes higher than the potential of the source S or drain A of the nch-MOSFET M, latch-up occurs as same as the case described above.
In particular, if an interface for the outer device of the semiconductor device is provided as the input terminal P1, it may be more probable that the potential of the input terminal P1 becomes lower than the potential of the emitter terminal P2. Although its period is shorter than the period to cause a surge, it is estimated that a larger stress may be applied to it due to a momentary current. Therefore, in this case also, it is probable that latch-up is caused.
So, when the protection circuit for protecting the input terminal P1 shown in FIG. 9 is used, it is prevented that parasitic devices occur between the protection circuit and the semiconductor substrate, by making the whole protection circuit as a device formed on the polysilicon. Thus, the emitter current flowing through the npn type parasitic transistor T2 is restrained by effects on the circuit so that it is prevented that the parasitic thyristor causes latch-up.
When the device is actually formed, a resistor R3 is certainly disposed in series for the npn type parasitic transistor T2 in which the source S or drain A of the nch-MOSFET M formed in the control circuit B1 acts as the emitter of the transistor T2. Thus it is restrained that the voltage between the resistor R3 and the emitter of the npn type parasitic transistor T2 is lowered, because the voltage of the Zener diode D8 in the forward direction is lowered. Similarly, it is designed such that the current of the circuit composed of the Zener diode D8, the resistor R3 and the control circuit B1 passes through the resistor R2 connected in series thereto. Thus the voltage drop caused in the above-mentioned circuit due to the resistor R2 is restrained, because the voltage of the Zener diode D1 in the forward direction is lowered.
In the conventional technique described above, the current flowing the parasitic device is restrained due to the voltage drop of the diode in the forward direction and the voltage drop at the series resistor in the circuit connected to the diode in parallel. Therefore, the voltage drop of the Zener diode D8 in the forward direction is smaller than the voltage between the base and the emitter of the npn type parasitic transistor T2 in the control circuit B1. In consequence, if the voltage drop of the Zener diode D1 in the forward direction is not smaller than that of the Zener diode D8, the effect to prevent the action of the parasitic thyristor may be smaller. Hereupon, in order to decrease the voltage drop of the diode in the forward direction using the same device, it is necessary to enlarge the area of the pn junction. Therefore the diode is formed in a considerably larger size in comparison with the circuit region to obtain a desired proof current.
In the conventional technique described above, the circuit region is composed of only the nch-MOSFET. Therefore, when the npn type parasitic transistor occurs, the area of the junction is smaller. In consequence, the voltage between the base and the emitter becomes comparatively larger. However, if it is intended to form the circuit region including the pch-MOSFET in the circuit forming process, the area of the junction becomes larger than that of the circuit including only the nch-MOSFET. Therefore, when the circuit for preventing the parasitic thyristor is formed, there may be required a larger protection circuit in comparison with the case of forming the circuit including only the nch-MOSFET. If the region of the protection circuit becomes larger as described above, the semiconductor device provided with the protection circuit becomes larger also. In consequence, it is feared that the cost for manufacturing the semiconductor device may increase.
The present invention has been developed to solve the aforementioned conventional problems, and its object is to provide a semiconductor device of a compact construction, in which an IGBT and a control circuit are formed in a same substrate, capable of effectively restraining the action of a parasitic device.
A semiconductor device according to the present invention developed for solving the aforementioned problems, is characterized in that if a pch-MOSFET is formed on a semiconductor substrate in which an IGBT has been formed, a circuit for preventing latch-up can have a smaller area in comparison with the conventional one by forming a diode using a diffused region which is necessary for forming the pch-MOSFET.
Namely, a Schottky barrier diode is formed on the semiconductor substrate in which the IGBT has been formed, and then the circuit for preventing the latch-up of the parasitic thyristor is formed by combining the Schottky barrier diode with a Zener diode formed on a polycrystalline silicon member. That is, it has a construction as follows. Namely, by using the Schottky barrier diode, a voltage in the forward direction, which is lower than the voltage between the base and the emitter of the npn type parasitic transistor of the circuit region, can be easily obtained with a smaller area. Thus, the circuit for preventing the latch-up of the parasitic thyristor is made smaller so that the semiconductor device can have a higher safety and a lower cost in comparison with the conventional one.
To put it concretely, a semiconductor device according to the present invention, in which an IGBT and a circuit region or circuit element for control use are formed on a same semiconductor substrate, is characterized in that it includes (i) a first diffused layer formed in the semiconductor substrate so as to be located near a surface of the semiconductor substrate, the first diffused layer having a conduction type different from that of the semiconductor substrate, (ii) a second diffused layer formed in the semiconductor substrate so as to be located near the surface of the semiconductor substrate, the second diffused layer being located within the first diffused layer, and the second diffused layer having a conduction type different from that of the first diffused layer, (iii) a first region formed on the second diffused layer, the first region being formed by removing a portion of an insulating film, (iv) a first metal wiring layer formed in the first region, (v) a third diffused layer located in the second diffused layer or located so as to intersect with the second diffused layer, the third diffused layer having a conduction type identical to that of the second diffused layer, (vi) a second region formed on the third diffused layer, the second region being formed by removing another portion of the insulating film, (vii) a second metal wiring layer formed in the second region, and (viii) a protection circuit formed by combining a Schottky barrier diode using the first and second metal wiring layers as electrodes and a Zener diode formed by depositing polycrystalline silicon on the insulating film on the semiconductor substrate, the protection circuit being connected to at least one of input terminals of the semiconductor device. Hereupon, the circuit region or circuit element is connected to the input terminal through the protection circuit and to a gate of the IGBT.
According to the semiconductor device of the present invention, for example, if a pch-MOSFET is formed on a semiconductor substrate in which an IGBT has been formed, a circuit for preventing latch-up can have a smaller area by forming a diode using the diffused region which is necessary for forming the pch-MOSFET. Namely, by using the Schottky barrier diode, a voltage in the forward direction, which is lower than the voltage between the base and the emitter of the npn type parasitic transistor of the circuit region, can be easily obtained with a smaller area. Thus, the circuit for preventing the latch-up of the parasitic thyristor is made smaller so that the semiconductor device can have a higher safety and a lower cost. That is, by using the Schottky barrier diode as the circuit for preventing latch-up of the parasitic thyristor, a higher effect to protect the circuit may be obtained with a smaller occupying area in comparison with the conventional case.
In the semiconductor device, each of the first and second metal wiring layers may be composed of aluminum or aluminum containing a minute quantity of other element. In this case, because the metal wiring layers are composed of aluminum or aluminum containing other element(s), the metal wiring layers may be easily formed so that the cost for manufacturing the semiconductor device may be lowered.
The semiconductor device may further include a fourth diffused layer formed so as to surround a junction between the second diffused layer and the first metal wiring layer. Hereupon, the fourth diffused layer preferably has a conduction type different from that of the second diffused layer. In this case, the performance of the semiconductor device may be improved by the fourth diffused layer.
In the semiconductor device, the Schottky barrier diode may include a first and second Schottky barrier diode members while the Zener diode may include a Zener diode member. Hereupon, a cathode of the Zener diode member and an anode of the first Schottky barrier diode member are preferably connected to the input terminal of the semiconductor device. A cathode of the first Schottky barrier diode member is preferably connected to a cathode of the second Schottky barrier diode member and to the circuit region or circuit element. An anode of the Zener diode member and an anode of the second Schottky barrier diode member are preferably connected to an emitter of the insulated gate bipolar transistor. In this case, the action of the parasitic transistor may be more effectively restrained by the above-mentioned circuit structure.
In the semiconductor device, the input terminal of the semiconductor device may be connected to one end portion of a resistor while the other end portion of the resistor is connected to the cathode of the Zener diode member and to the anode of the first Schottky barrier diode member. In this case, the action of the parasitic transistor may be further more effectively restrained by the resistor disposed between the first Zener diode member and the first Schottky barrier diode member.
In the semiconductor device, the Zener diode may include a further Zener diode member. Hereupon, an anode of the further Zener diode member is preferably connected to the anode of the Zener diode member. A cathode of the further Zener diode member is preferably connected to the emitter of the IGBT. In this case, the action of the parasitic transistor may be more effectively restrained by the above-mentioned circuit structure.
The semiconductor device may further include one or more input terminal. Hereupon, the semiconductor device may include at least one circuit having a construction as same as that of the circuit composed of the Zener diode member and the first and second Schottky barrier diode members. In this case, the function of the semiconductor device may be improved, because it is provided with a plurality of input terminals and protection circuits.
In the semiconductor device, the fourth diffused layer may be composed of a diffusion layer used for forming the IGBT. In this case, because the fourth diffused layer is formed by utilizing the diffusion layer used for forming the IGBT, the process for manufacturing the semiconductor device may be simplified so that the cost for manufacturing it may be lowered.
The semiconductor device may further include a metal-diffused layer located between the second diffused layer and the first metal wiring layer. The metal-diffused layer is preferably formed by diffusing or depositing a metal between the second diffused layer and the first metal wiring layer. Hereupon, the diffused or deposited metal is different from the metal composing the first metal wiring layer. In this case, the action of the parasitic transistor may be much more effectively restrained by the metal-diffused layer.
In the semiconductor device, the diffused or deposited metal may be platinum. In this case, the voltage applied to the input terminal may be transmitted to the circuit region or circuit element with a smaller voltage loss.